In contrast to conventional planar metal-oxide-semiconductor field-effect transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved. One known type of non-planar, multi-gate transistor, commonly referred to as a “FinFET,” includes two or more parallel fin structures (the “fins”) formed on a substrate, such as a silicon-on-insulator substrate. The fins extend along a first axis between common source and drain electrodes. At least one conductive gate structure (the “gate”) is formed over the fins and extends along a second axis generally perpendicular to the first axis. More specifically, the gate extends across and over the fins such that an intermediate portion of the gate conformally overlays three surfaces of each fin (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of each fin).
While providing the advantages noted above, FinFETs and other non-planar multi-gate devices (e.g., triFETs) can be somewhat difficult to fabricate due to their unique topographies. For example, in the case of a simplified FinFET including two fins and one gate, it is difficult to form sidewall spacers adjacent opposing sidewalls of the gate without simultaneously forming parasitic sidewall spacers adjacent opposing sidewalls of the fins. In one known fabrication technique, at least one layer of spacer material (e.g., silicon nitride or silicon oxide) is blanket deposited over the fins and the gate. One or more etching steps are then performed to remove the spacer material adjacent the fins while leaving intact portions of the spacer material adjacent opposing sidewalls of the gate. The remaining portions of the spacer material adjacent the gate thus serve as sidewall spacers in subsequent fabrication processes.
While permitting the selective formation of sidewall spacers adjacent a gate, the above-described fabrication technique is limited in several respects. Most notably, in the above-described fabrication technique, the etching process is typically required to continue significantly beyond the traditional etch endpoint (i.e., a prolonged over-etch is performed) to ensure that the spacer material adjacent opposing sidewalls of the fins is removed in its entirety. In many cases, the over-etch may approach or exceed 400% of ideal thickness removal. Due to its severity, this over-etch has several undesirable consequences. First, a considerable volume of spacer material is removed from the gate during the etching process thus potentially exposing the fin-gate intersection. Although the height of the gate may be increased to ensure that the etch does reach the fin-gate intersection, an increase in gate height results in a corresponding increase in gate capacitance. Second, the prolonged over-etch may remove an excessive volume of hardmask material overlying the gate structure, which can render subsequent selective epitaxial growth processes more difficult. Third, exposure of the substrate to prolonged over-etching may undercut the fins and thus remove structure support therefrom. Fourth, the source/drain area of the fins' sidewalls can be undesirably roughened or otherwise damaged by prolonged exposure to over-etching. Fifth, prolonged over-etching may result in significant variations in the dimensions (e.g., width) of the final sidewall spacers. Finally, as a still further limitation, prolonged over-etching removes dielectric material overlying the fins, which renders subsequent usage of the dielectric material as a strain layer more difficult.
There thus exists an ongoing need to provide embodiments of a method for fabricating a non-planar semiconductor device, such as a FinFET, wherein sidewall spacers are formed adjacent the gate without simultaneously forming sidewall spacer adjacent the fins that minimizes or eliminates over-etching requirements. More generally, there exists an ongoing need to provide embodiments of a method for forming sidewall spacers adjacent selected surfaces on a non-planar semiconductor device or other small scale electronic device that includes first and second raised structures extending along substantially perpendicular axes. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and this Background.